module data_synchronizer (
    input  wire        clk,
    input  wire        rst_n,
    input  wire        frame_sync,
    input  wire [23:0] mic_data_in [15:0],
    
    output wire [23:0] mic_data_sync [15:0],
    output wire        data_ready,
    output wire [15:0] sync_status    // 各通道同步状态
);

// 输入数据锁存
reg [23:0] data_buffer [15:0];
reg        buffer_valid;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        buffer_valid <= 1'b0;
    end 
    else if (frame_sync) begin
        for (int i = 0; i < 16; i = i + 1) begin
            data_buffer[i] <= mic_data_in[i];
        end
        buffer_valid <= 1'b1;
    end 
    else begin
        buffer_valid <= 1'b0;
    end
end

// 同步数据输出
assign mic_data_sync = data_buffer;
assign data_ready = buffer_valid;

endmodule